1. Field of the Invention
This invention relates generally to the testing of digital signal processing units and, more particularly, to the detection of trigger events in a target processor that result in the generation of a trigger signals. The trigger events are related to the program execution and information related to these events is used by the host processing unit to analyze the operation of the target processor by the host processing unit.
2. Description of the Related Art
As microprocessors and digital signal processors have become increasingly complex, advanced techniques have been developed to test these devices. Dedicated apparatus is available to implement the advanced techniques. Referring to FIG. 1A, a general configuration for the test and debug of a target processor 12 is shown. The test and debug procedures operate under control of a host processing unit 10. The host processing unit 10 applies control signals to the emulation unit 11 and receives (test) data signals from the emulation unit 11 by cable connector 14. The emulation unit 11 applies control signals to and receives (test) signals from the target processor 12 by connector cable 15. The emulation unit 11 can be thought of as an interface unit between the host processing unit 10 and the target processor 12. The emulation unit 11 must process the control signals from the host processor unit 10 and apply these signals to the target processor 12 in such a manner that the target processor will respond with the appropriate test signals. The test signals from the target processor 12 can be a variety types. Two of the most popular test signal types are the JTAG (Joint Test Action Group) signals and trace signals. The JTAG signal provides a standardized test procedure in wide use. Trace signals are signals from a multiplicity of junctions in the target processor 12. While the width of the bus interfacing to the host processing unit 10 generally have a standardized width, the bus between the emulation unit 11 and the target processor 12 can be increased to accommodate the increasing complexity of the target processing unit 12. Thus, part of the interface function between the host processing unit 10 and the target processor 12 is to store the test signals until the signals can be transmitted to the host processing unit 10.
Referring to FIG. 1B, the operation of the trigger generation unit 19 is shown. At least one event signal is applied to the trigger generation unit 19. Based on the event signals applied to the trigger generation unit 19, a trigger signal is selected. Certain events and combination of events, referred to as an event front, generate a selected trigger signal that results in certain activity in the target processor such as a debug halt. Combinations of different events generating trigger signals are referred to as jobs. Multiple jobs can have the same trigger signal or combination of trigger signals. In the test and debug of the target processor, the trigger signals can provide impetus for changing state in the target processor or for performing a specified activity. The event front defines the reason for the generation of trigger signal. This information is important in understanding the operation of the target processor because, as pointed out above, several combinations of events can result in the generation of a trigger signal. In order to analyze the operation of the target processing unit, the portion of the code resulting in the trigger signal must be identified. However, the events in the host processor leading to the generation of event signals can be complicated. Specifically, the characteristics of an instruction at a program counter address can determine whether a trigger signal should be generated. A trigger signal can indicate when an address is within a range of addresses, outside of a range of addresses, some combination of address characteristics, and/or the address is aligned with a reference address. In this instance, the address can be the program address of an instruction or a memory address directly or indirectly referenced by a program instruction.
A need has been felt for apparatus and an associated method having the feature that events corresponding to characteristics of the program counter address can be identified. It would be yet another feature of the apparatus and associated method to provide for the identification of program counter address characteristics that encompasses more than one range. It would be a still further feature of the present invention to identify program address characteristics that include the characteristics of the data identified by the program counter address. It would be still another feature of the apparatus and associated method to identify characteristics of addresses referenced by program instruction. It would be yet a further feature of the present invention to compare characteristics of two addresses.